ST STM32G4 Series Reference Manual page 1932

FD controller area network (FDCAN)
43.4 FDCAN registers
43.4.1 FDCAN core release register (FDCAN_CREL)
Address offset: 0x0000
Reset value: 0x3214_1218
31 30 29
REL[3:0]
r r r
15 14 13
r r r
Bits 31: 28 REL: 3
Bits 27: 24 STEP: 2
Bits 23: 20 SUBSTEP: 1
Bits 19: 16 YEAR: 4
Bits 15: 8 MON: 12
Bits 7: 0 DAY: 18
43.4.2 FDCAN Endian register (FDCAN_ENDN)
Address offset: 0x0004
Reset value: 0x8765_4321
31 30 29
r r r
15 14 13
r r r
Bits 31: 0 ETV: Endiannes Test Value
43.4.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP)
Address offset: 0x000C
Reset value: 0x0000 0A33
This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN time
quantum may be programmed in the range of 1 to 32 FDCAN clock periods. tq = (DBRP + 1)
FDCAN clock period.
1932/2083
28 27 26 25
STEP[3:0]
r r r r
12 11 10 9
MON[7:0]
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
The endianness test value is 0x8765 4321.
24 23 22
SUBSTEP[3:0]
r r r
8 7 6
r r r
24 23 22
ETV[31:16]
r r r
8 7 6
ETV[15:0]
r r r
RM0440 Rev 1
21 20 19 18
YEAR[3:0]
r r r r
5 4 3 2
DAY[7:0]
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0440
17 16
r r
1 0
r r
17 16
r r
1 0
r r