ST STM32G4 Series Reference Manual page 1942

FD controller area network (FDCAN)
Bit 5 EP: Error Passive
Bits 4: 3 ACT: Activity
Bits 2: 0 LEC: Last Error Code
Note: When a frame in FDCAN format has reached the data phase with BRS flag set, the next
CAN event (error or valid frame) will be shown in FLEC instead of LEC. An error in a fixed
stuff bit of a FDCAN CRC sequence will be shown as a Form Error, not Stuff Error.
Note: The Bus_Off recovery sequence (see CAN Specification Rev. 2.0 or ISO11898-1) cannot be
shortened by setting or resetting CCCR[INIT]. If the device goes Bus_Off, it will set
CCCR.INIT of its own, stopping all bus activities. Once CCCR[INIT] has been cleared by the
CPU, the device will then wait for 129 occurrences of Bus Idle (129 × 11 consecutive
recessive bits) before resuming normal operation. At the end of the Bus_Off recovery
sequence, the Error Management Counters will be reset. During the waiting time after the
reset of CCCR[INIT], each time a sequence of 11 recessive bits has been monitored, a Bit0
Error code is written to PSR[LEC], enabling the CPU to readily check up whether the CAN
bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery
sequence. ECR[REC] is used to count these sequences.
1942/2083
0: The FDCAN is in the Error_Active state. It normally takes part in bus communication
and sends an active error flag when an error has been detected
1: The FDCAN is in the Error_Passive state
Monitors the module's CAN communication state.
00: Synchronizing: node is synchronizing on CAN communication
01: Idle: node is neither receiver nor transmitter
10: Receiver: node is operating as receiver
11: Transmitter: node is operating as transmitter
The LEC indicates the type of the last error to occur on the CAN bus. This field will be
cleared to 0 when a message has been transferred (reception or transmission) without
error.
000: No Error: No error occurred since LEC has been reset by successful reception or
transmission.
001: Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a
received message where this is not allowed.
010: Form Error: A fixed format part of a received frame has the wrong format.
011: AckError: The message transmitted by the FDCAN was not acknowledged by
another node.
100: Bit1Error: During the transmission of a message (with the exception of the
arbitration field), the device wanted to send a recessive level (bit of logical value 1), but
the monitored bus value was dominant.
101: Bit0Error: During the transmission of a message (or acknowledge bit, or active
error flag, or overload flag), the device wanted to send a dominant level (data or
identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off
recovery this status is set each time a sequence of 11 recessive bits has been
monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery
sequence (indicating the bus is not stuck at dominant or continuously disturbed).
110: CRCError: The CRC check sum of a received message was incorrect. The CRC of
an incoming message does not match with the CRC calculated from the received data.
111: NoChange: Any read access to the Protocol status register re-initializes the LEC to
'7'. When the LEC shows the value '7', no CAN bus event was detected since the last
CPU read access to the Protocol status register.
Access type is RS: set on read.
RM0440 Rev 1
RM0440