ST STM32G4 Series Reference Manual page 1934

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32G4 Series:

Table of Contents

FD controller area network (FDCAN)

Bits 31: 8 Reserved, must be kept at reset value.

Bit 7 RX: Receive Pin

Bits 6: 5 TX: Control of Transmit Pin

Bit 4 LBCK: Loop Back mode

Bits 3: 0 Reserved, must be kept at reset value.

FDCAN RAM watchdog register (FDCAN_RWD)

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM

access starts the Message RAM Watchdog Counter with the value configured by the

RWD[WDC] bits.

The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful

completion by activating its READY output. In case there is no response from the Message

RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI]

bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.

Address offset: 0x0014

Reset value: 0x0000 0000

Monitors the actual value of pin FDCANx_RX

0: The CAN bus is dominant (FDCANx_RX = 0)

1: The CAN bus is recessive (FDCANx_RX = 1)

00: Reset value, FDCANx_TX TX is controlled by the CAN core, updated at the end of the

CAN bit time

01: Sample point can be monitored at pin FDCANx_TX

10: Dominant (0) level at pin FDCANx_TX

11: Recessive (1) at pin FDCANx_TX

0: Reset value, Loop Back mode is disabled

1: Loop Back mode is enabled (see

Power down (Sleep

RM0440 Rev 1

Chapters

Table of Contents

Do you have a question about the STM32G4 Series and is the answer not in the manual?