ST STM32G4 Series Reference Manual page 1954

Advanced arm-based 32-bit mcus

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FD controller area network (FDCAN)

FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A)

Address offset: 0x009C

Reset value: 0x0000 0000

Bits 31: 3 Reserved, must be kept at reset value.

Bits 2: 0 F1AI: Rx FIFO 1 Acknowledge Index

FDCAN Tx buffer configuration register (FDCAN_TXBC)

Address offset: 0x00C0

Reset value: 0x0000 0000

Bits 31: 25 Reserved, must be kept at reset value.

Bit 24 TFQM: Tx FIFO/Queue Mode.

Bits 23: 0 Reserved, must be kept at reset value.

FDCAN Tx FIFO / queue status register (FDCAN_TXFQS)

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP.

Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan

(TXBRP not yet updated).

Address offset: 0x00C4

Reset value: 0x0000 0003

After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to

write the buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx

FIFO 1 Get Index RXF1S[F1GI] to F1AI + 1 and update the FIFO 1 Fill Level

RXF1S[F1FL].

0: Tx FIFO operation

1: Tx Queue operation.

This is a protected write (P) bit, which means that write access by the bits is possible only

when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

RM0440 Rev 1

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