ST STM32G4 Series Reference Manual page 1939

RM0440
Bits 31: 16 Reserved, must be kept at reset value.
Bits 15: 0 TSC: Timestamp Counter
Note: A "wrap around" is a change of the Timestamp Counter value from non-0 to 0 that is not
caused by write access to TSCV.
43.4.10 FDCAN timeout counter configuration register (FDCAN_TOCC)
Address offset: 0x0028
Reset value: 0xFFFF 0000
31 30 29
rw rw rw
15 14 13
Res. Res. Res. Res.
Bits 31: 16 TOP: Timeout Period
Bits 15: 3 Reserved, must be kept at reset value.
Bits 2: 1 TOS: Timeout Select
Bit 0 ETOC: Enable Timeout Counter
For more details see
43.4.11 FDCAN timeout counter value register (FDCAN_TOCV)
Address offset: 0x002C
Reset value: 0x0000 FFFF
The internal/external Timestamp Counter value is captured on start of frame (both Rx and
Tx). When TSCC[TSS] = '01', the Timestamp Counter is incremented in multiples of CAN
bit times [1 ... 16] depending on the configuration of TSCC[TCP]. A wrap around sets
interrupt flag IR[TSW]. Write access resets the counter to 0. When TSCC.TSS = 10, TSC
reflects the external Timestamp Counter value. A write access has no impact.
28 27 26 25
rw rw rw rw
12 11 10 9
Res. Res. Res.
Start value of the Timeout Counter (down-counter). Configures the Timeout Period.
When operating in Continuous mode, a write to TOCV presets the counter to the value
configured by TOCC[TOP] and continues down-counting. When the Timeout Counter is
controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured
by TOCC[TOP]. Down-counting is started when the first FIFO element is stored.
00: Continuous operation
01: Timeout controlled by Tx Event FIFO
10: Timeout controlled by Rx FIFO 0
11: Timeout controlled by Rx FIFO 1
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and
bit 0 [INIT] of CCCR register are set to 1.
0: Timeout Counter disabled
1: Timeout Counter enabled
This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit
0 [INIT] of CCCR register are set to 1.
Timeout counter.
FD controller area network (FDCAN)
24 23 22
TOP[15:0]
rw rw rw
8 7 6
Res. Res. Res.
RM0440 Rev 1
21 20 19 18
rw rw rw rw
5 4 3 2
Res. Res. Res. TOS[1:0]
rw
17 16
rw rw
1 0
ETOC
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