ST STM32G4 Series Reference Manual page 1946

FD controller area network (FDCAN)
43.4.16 FDCAN interrupt enable register (FDCAN_IE)
The settings in the Interrupt enable register determine which status changes in the Interrupt
register will be signaled on an interrupt line.
Address offset: 0x0054
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
TOOE MRAFE TSWE TEFLE TEFFE TEFNE
rw rw rw
Bits 31: 24 Reserved, must be kept at reset value.
Bit 23 ARAE: Access to Reserved Address Enable
Bit 22 PEDE: Protocol Error in Data Phase Enable
Bit 21 PEAE: Protocol Error in Arbitration Phase Enable
Bit 20 WDIE: Watchdog Interrupt Enable
Bit 19 BOE: Bus_Off Status
Bit 18 EWE: Warning Status Interrupt Enable
Bit 17 EPE: Error Passive Interrupt Enable
Bit 16 ELOE: Error Logging Overflow Interrupt Enable
Bit 15 TOOE: Timeout Occurred Interrupt Enable
Bit 14 MRAFE: Message RAM Access Failure Interrupt Enable
Bit 13 TSWE: Timestamp Wraparound Interrupt Enable
1946/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
TFEE
rw rw rw rw
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
0: Interrupt disabled
1: Interrupt enabled
24 23 22
Res. ARAE PEDE PEAE
rw rw
8 7 6
TCFE TCE HPME RF1LE RF1FE RF1NE RF0LE RF0FE RF0NE
rw rw rw
RM0440 Rev 1
21 20 19 18
WDIE BOE EWE
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0440
17 16
EPE ELOE
rw rw
1 0
rw rw