ST STM32G4 Series Reference Manual page 1937

RM0440
43.4.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP)
Address offset: 0x001C
Reset value: 0x0600 0A03
This register is only writable if bits CCCR[CCE] and CCCR[INIT] are set. The CAN bit time
may be programed in the range of 4 to 81 tq. The CAN time quantum may be programmed
in the range of [1 ... 1024] FDCAN kernel clock periods.
tq = (BRP + 1) FDCAN clock period fdcan_clk
NTSEG1 is the sum of Prop_Seg and Phase_Seg1. NTSEG2 is Phase_Seg2. Therefore the
length of the bit time is (programmed values) [NTSEG1 + NTSEG2 + 3] tq or (functional
values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq.
The Information Processing Time (IPT) is 0, meaning the data for the next bit is available at
the first clock edge after the sample point.
31 30 29
NSJW[6:0]
rw rw rw
15 14 13
rw rw rw
Bits 31: 25 NSJW: Nominal (Re)Synchronization Jump Width
Bits 24: 16 NBRP: Bit Rate Prescaler
Bits 15: 8 NTSEG1: Nominal Time segment before sample point
Bit 7 Reserved, must be kept at reset value.
Bits 6: 0 NTSEG2: Nominal Time segment after sample point
Note: With a CAN kernel clock of 48 MHz, the reset value of 0x06000A03 configures the FDCAN
for a bit rate of 171 kbit/s.
28 27 26 25
rw rw rw rw
12 11 10 9
NTSEG1[7:0]
rw rw rw rw
Valid values are 0 to 127. The actual interpretation by the hardware of this value is such
that the used value is the one programmed incremented by one.
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and
bit 0 [INIT] of CCCR register are set to 1.
Value by which the oscillator frequency is divided for generating the bit time quanta. The
bit time is built up from a multiple of this quanta. Valid values are 0 to 511. The actual
interpretation by the hardware of this value is such that one more than the value
programmed here is used.
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and
bit 0 [INIT] of CCCR register are set to 1.
Valid values are 0 to 255. The actual interpretation by the hardware of this value is such
that one more than the programmed value is used.
These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and
bit 0 [INIT] of CCCR register are set to 1.
Valid values are 0 to 127. The actual interpretation by the hardware of this value is such
that one more than the programmed value is used.
FD controller area network (FDCAN)
24 23 22
rw rw rw
8 7 6
Res.
rw rw rw
RM0440 Rev 1
21 20 19 18
NBRP[8:0]
rw rw rw rw
5 4 3 2
NTSEG2[6:0]
rw rw rw rw
17 16
rw rw
1 0
rw rw
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