ST STM32G4 Series Reference Manual page 1955

Advanced arm-based 32-bit mcus

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Bit 31: 22 Reserved, must be kept at reset value.

Bit 21 TFQF: Tx FIFO/Queue Full

Bit 20: 18 Reserved, must be kept at reset value.

Bits 17: 16 TFQPI: Tx FIFO/Queue Put Index

Bits 15: 10 Reserved, must be kept at reset value.

Bits 9: 8 [TFGI:

Bits 7: 3 Reserved, must be kept at reset value.

Bits 2: 0 TFFL: Tx FIFO Free Level

FDCAN Tx buffer request pending register (FDCAN_TXBRP)

Address offset: 0x00C8

Reset value: 0x0000 0000

0: Tx FIFO/Queue not full

1: Tx FIFO/Queue full

Tx FIFO/Queue write index pointer, range 0 to 3

Tx FIFO Get Index.

Tx FIFO read index pointer, range 0 to 3. Read as 0 when Tx Queue operation is

configured (TXBC.TFQM = 1)

Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 3. Read as 0

when Tx Queue operation is configured (TXBC[TFQM] = 1).

FD controller area network (FDCAN)

RM0440 Rev 1

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