ST STM32G4 Series Reference Manual page 1938

Advanced arm-based 32-bit mcus

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FD controller area network (FDCAN)

FDCAN timestamp counter configuration register (FDCAN_TSCC)

Address offset: 0x0020

Reset value: 0x0000 0000

Bits 31: 20 Reserved, must be kept at reset value.

Bits 19: 16 TCP: Timestamp Counter Prescaler

Bits 15: 2 Reserved, must be kept at reset value.

Bits 1: 0 TSS: Timestamp Select

FDCAN timestamp counter value register (FDCAN_TSCV)

Address offset: 0x0024

Reset value: 0x0000 0000

Configures the timestamp and timeout counters time unit in multiples of CAN bit times

The actual interpretation by the hardware of this value is such that one more than the

value programmed here is used.

In CAN FD mode the internal timestamp counter TCP does not provide a constant time

base due to the different CAN bit times between arbitration phase and data phase. Thus

CAN FD requires an external counter for timestamp generation (TSS = 10).

These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and

bit 0 [INIT] of CCCR register are set to 1.

00: Timestamp counter value always 0x0000

01: Timestamp counter value incremented according to TCP

10: External timestamp counter from TIM3 value (tim3_cnt[0:15])

11: Same as 00.

These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and

bit 0 [INIT] of CCCR register are set to 1.

RM0440 Rev 1

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