ST STM32G4 Series Reference Manual page 1948

FD controller area network (FDCAN)
Address offset: 0x0058
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31: 7 Reserved, must be kept at reset value.
Bit 6 PERR: Protocol error group the following interruption
Bit 5 :BERR: Bit and Line error group the following interruption
Bit 4 MISC: This interrupt regroup the following interrupt
Bit 3 TFERR: Tx FIFO ERROR group the following interruption
Bit 2 SMSG: Status message bit group the following interruption
Bit 1 RxFIFO1: RX FIFO bit group the following interruption
Bit 0 RxFIFO0: RX FIFO bit group the following interruption
43.4.18 FDCAN interrupt line enable register (FDCAN_ILE)
Each of the two interrupt lines to the CPU can be enabled/disabled separately by
programming bits EINT0 and EINT1.
1948/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
ARAL: Access to Reserved Address Line
PEDL: Protocol Error in Data Phase Line
PEAL: Protocol Error in Arbitration Phase Line
WDIL: Watchdog Interrupt Line
BOL: Bus_Off Status
EWL: Warning Status Interrupt Line
EPL Error Passive Interrupt Line
ELOL: Error Logging Overflow Interrupt Line
TOOL: Timeout Occurred Interrupt Line
MRAFL: Message RAM Access Failure Interrupt Line
TSWL: Timestamp Wraparound Interrupt Line
TEFLL: Tx Event FIFO Element Lost Interrupt Line
TEFFL: Tx Event FIFO Full Interrupt Line
TEFNL: Tx Event FIFO New Entry Interrupt Line
TFEL: Tx FIFO Empty Interrupt Line
TCFL: Transmission Cancellation Finished Interrupt Line
TCL: Transmission Completed Interrupt Line
HPML: High Priority Message Interrupt Line
RF1LL: Rx FIFO 1 Message Lost Interrupt Line
RF1FL: Rx FIFO 1 Full Interrupt Line
RF1NL: Rx FIFO 1 New Message Interrupt Line
RF0LL: Rx FIFO 0 Message Lost Interrupt Line
RF0FL: Rx FIFO 0 Full Interrupt Line
RF0NL: Rx FIFO 0 New Message Interrupt Line
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. PERR BERR
rw rw
RM0440 Rev 1
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
MISC TFERR SMSG RxFIFO1 RxFIFO0
rw rw rw rw
RM0440
16
Res.
0
rw