ST STM32G4 Series Reference Manual page 1943

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32G4 Series:

Table of Contents

FDCAN transmitter delay compensation register (FDCAN_TDCR)

Address offset: 0x0048

Reset value: 0x0000 0000

Bits 31: 15 Reserved, must be kept at reset value.

Bits 14: 8 TDCO: Transmitter Delay Compensation Offset

Bit 7 Reserved, must be kept at reset value.

Bits 6: 0 TDCF: Transmitter Delay Compensation Filter Window Length

FDCAN interrupt register (FDCAN_IR)

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags

remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit

Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls

whether an interrupt is generated. The configuration of ILS controls on which interrupt line

an interrupt is signaled.

Address offset: 0x0050

Reset value: 0x0000 0000

Offset value defining the distance between the measured delay from FDCAN_TX to

FDCAN_RX and the secondary sample point. Valid values are 0 to 127 mtq.

These are protected write (P) bits, which means that write access by the bits is possible

only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

Defines the minimum value for the SSP position, dominant edges on FDCAN_RX that

would result in an earlier SSP position are ignored for transmitter delay measurements.

These are protected write (P) bits, which means that write access by the bits is possible

only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.

FD controller area network (FDCAN)

RM0440 Rev 1

Chapters

Table of Contents

Do you have a question about the STM32G4 Series and is the answer not in the manual?