System Control Register 2 (Syscr2); Ram Emulation Register (Ramer) - Renesas H8S/2319 series Hardware Manual

17.14.5 System Control Register 2 (SYSCR2)

Bit : 7
—
Initial value : 0
R/W : —
SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control.
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 can only be used in the F-ZTAT version. In the mask ROM version this register will
return an undefined value if read, and cannot be modified.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit
enables the flash memory control registers to be read and written to. Clearing FLSHE to 0
designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE Description
0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
1 Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: Only 0 should be written.

17.14.6 RAM Emulation Register (RAMER)

Bit : 7
—
Initial value : 0
R/W : —
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
6 5
— — —
0 0
— — —
6 5
— — —
0 0
— — —
4 3 2
FLSHE —
0 0 0
R/W —
4 3 2
RAMS RAM2
0 0 0
R/W R/W
Rev. 5.00, 12/03, page 629 of 1088
1 0
— —
0 0
— R/W
(Initial value)
1 0
RAM1 RAM0
0 0
R/W R/W