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8.11.2
Register Configuration
Table 8-19 shows the port F register configuration.
Table 8-19 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Bus control register L
System control register
Port function control register 1
Port function control register 2
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
:
7
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6 *
Initial value :
1
R/W
:
W
Mode 7 *
Initial value :
0
R/W
:
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6 * , and to
H'00 in mode 7 * . It retains its prior state after in software standby mode. The OPE bit in SBYCR
is used to select whether the bus control output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Note: * Modes 6 and 7 are not available in the ROMless versions.
Abbreviation
PFDDR
PFDR
PORTF
BCRL
SYSCR
PFCR1
PFCR2
6
5
0
0
W
W
0
0
W
W
R/W
Initial Value
H'80/H'00 *
W
R/W
H'00
R
Undefined
R/W
H'3C
R/W
H'01
R/W
H'0F
R/W
H'30
4
3
0
0
W
W
0
0
W
W
Rev. 5.00, 12/03, page 279 of 1088
Address *
2
H'FEBE
H'FF6E
H'FF5E
H'FED5
H'FF39
H'FF45
H'FFAC
2
1
0
0
W
W
0
0
W
W
1
0
0
W
0
W
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