Renesas H8S/2319 series Hardware Manual page 404

Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
2
write is not performed.
Figure 9-49 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT
Figure 9-49 Contention between TCNT Write and Clear Operations
Rev. 5.00, 12/03, page 374 of 1088
TCNT write cycle
T T
1 2
TCNT address
N H'0000