Table of Contents
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15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ....................................................... 542
15.2.2 D/A Control Registers 01 (DACR01) .................................................................. 542
15.2.3 Module Stop Control Register (MSTPCR) .......................................................... 544
15.3 Operation .......................................................................................................................... 545
16.1 Overview........................................................................................................................... 547
16.1.1 Block Diagram..................................................................................................... 547
16.1.2 Register Configuration......................................................................................... 548
16.2 Register Descriptions ........................................................................................................ 548
16.2.1 System Control Register (SYSCR) ...................................................................... 548
16.3 Operation .......................................................................................................................... 549
16.4 Usage Note........................................................................................................................ 549
17.1 Overview........................................................................................................................... 551
17.1.1 Block Diagram..................................................................................................... 551
17.1.2 Register Configuration......................................................................................... 552
17.2 Register Descriptions ........................................................................................................ 552
17.2.1 Mode Control Register (MDCR) ......................................................................... 552
17.2.2 Bus Control Register L (BCRL) .......................................................................... 553
17.3 Operation .......................................................................................................................... 553
H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) ......................................................................... 557
17.4.1 Features................................................................................................................ 557
17.4.2 Overview.............................................................................................................. 558
17.4.3 Flash Memory Operating Modes ......................................................................... 559
17.4.4 On-Board Programming Modes........................................................................... 560
17.4.5 Flash Memory Emulation in RAM ...................................................................... 562
17.4.6 Differences between Boot Mode and User Program Mode ................................. 563
17.4.7 Block Configuration............................................................................................. 564
17.4.8 Pin Configuration................................................................................................. 565
17.4.9 Register Configuration......................................................................................... 566
17.5 Register Descriptions ........................................................................................................ 567
17.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 567
17.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 570
17.5.3 Erase Block Register 1 (EBR1) ........................................................................... 571
17.5.4 Erase Block Register 2 (EBR2) ........................................................................... 571
17.5.5 System Control Register 2 (SYSCR2) ................................................................. 572
17.5.6 RAM Emulation Register (RAMER)................................................................... 573
17.6 On-Board Programming Modes........................................................................................ 575
17.6.1 Boot Mode ........................................................................................................... 575
17.6.2 User Program Mode............................................................................................. 581
.................................................................................................................. 547
.................................................................................................................. 551
Rev. 5.00, 12/03, page xxiii of xxx
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