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16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access
space. When a 16-bit access space is accessed, the upper half (D
for the even address, and the lower half (D
Wait states cannot be inserted.
Read
Write
Note: n = 0 to 7
Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)
Rev. 5.00, 12/03, page 162 of 1088
to D
7
φ
Address bus
CSn
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
to D
15
) for the odd address.
0
Bus cycle
T
1
High
Valid
High impedance
) of the data bus is used
8
T
2
Valid
Invalid
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