Renesas H8S/2319 series Hardware Manual page 304

Port E Data Register (PEDR)
Bit : 7
PE7DR
Initial value : 0
R/W : R/W
PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to
PE0).
PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port E Register (PORTE)
Bit : 7
PE7
— *
Initial value :
R/W : R
Note: * Determined by state of pins PE7 to PE0.
PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port E pins (PE7 to PE0) must always be performed on PEDR.
If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E
read is performed while PEDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as
PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.
Rev. 5.00, 12/03, page 274 of 1088
6 5
PE6DR PE5DR PE4DR
0 0
R/W R/W
6 5
PE6 PE5
— * — *
R R
4 3
PE3DR PE2DR
0 0
R/W R/W R/W
4 3
PE4 PE3 PE2
— * — *
R R
2 1
PE1DR PE0DR
0 0
R/W R/W
2 1
PE1 PE0
— * — * — *
R R
0
0
0
R