Renesas H8S/2319 series Hardware Manual page 935

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals
during execution of the above instruction with an 8-bit bus, using three-state access with no wait
states.
φ
Address bus
RD
HWR, LWR
of instruction
Figure A-1 Address Bus, RD
R:W 2nd
Fetching Fetching
3rd byte 4th byte
of instruction
(8-Bit Bus, Three-State Access, No Wait States)
High
Internal
operation
Fetching
1st byte of
instruction at
jump address
RD RD, HWR RD HWR, and LWR HWR HWR LWR Timing LWR LWR
Rev. 5.00, 12/03, page 905 of 1088
R:W EA
Fetching
2nd byte of
instruction at
jump address