Renesas H8S/2319 series Hardware Manual page 871

Renesas 16-bit single-chip microcomputer
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(3) Bus Timing
Table 20-34 Bus Timing
Condition B: V
= 3.0 V to 3.6 V, AV
CC
0 V, φ = 2 MHz to 25 MHz, T
T
= –40°C to 85°C (wide-range specifications)
a
Item
Address delay time
Address setup time
Address hold time
CS delay time 1
AS delay time
RD delay time 1
RD delay time 2
Read data setup time
Read data hold time
Read data access time 1
Read data access time 2
Read data access time 3
Read data access time 4
Read data access time 5
WR delay time 1
WR delay time 2
WR pulse width 1
WR pulse width 2
Write data delay time
Write data setup time
Write data hold time
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus floating time
BREQO delay time
= 3.0 V to 3.6 V, V
CC
= –20°C to 75°C (regular specifications),
a
Symbol
Min
t
AD
0.5 × t
t
– 15
AS
cyc
0.5 × t
t
– 8
AH
cyc
t
CSD1
t
ASD
t
RSD1
t
RSD2
t
15
RDS
t
0
RDH
t
ACC1
t
ACC2
t
ACC3
t
ACC4
t
ACC5
t
WRD1
t
WRD2
1.0 × t
t
– 15
WSW1
cyc
1.5 × t
t
– 15
WSW2
cyc
t
WDD
0.5 × t
t
– 15
WDS
cyc
0.5 × t
t
– 8
WDH
cyc
t
25
WTS
t
5
WTH
t
30
BRQS
t
BACD
t
BZD
t
BRQOD
= 3.0 V to AV
ref
Max
Unit
20
ns
ns
ns
15
ns
15
ns
15
ns
15
ns
ns
ns
1.0 × t
– 20
ns
cyc
1.5 × t
– 20
ns
cyc
2.0 × t
– 20
ns
cyc
2.5 × t
– 20
ns
cyc
3.0 × t
– 20
ns
cyc
15
ns
15
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
15
ns
40
ns
25
ns
Rev. 5.00, 12/03, page 841 of 1088
— Preliminary —
, V
= AV
=
CC
SS
SS
Test Conditions
Figures 20-6 to 20-10
Figure 20-8
Figure 20-11
Figure 20-12

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