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TSR3—Timer Status Register 3
Bit
:
7
Initial value
:
1
Read/Write
:
Note: * Can only be written with 0 for flag clearing.
Rev. 5.00, 12/03, page 950 of 1088
6
5
4
3
TCFV
TGFD
1
0
0
0
R/(W)*
R/(W)*
Input Capture/Output Compare Flag D
0
1
Overflow Flag
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
2
1
0
TGFC
TGFB
TGFA
0
0
0
R/(W)*
R/(W)*
R/(W)*
Input Capture/Output Compare Flag A
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When 0 is written to TGFA after reading TGFA = 1
1
[Setting conditions]
• When TCNT=TGRA while TGRA is function-
• When TCNT value is transferred to TGRA by
Input Capture/Output Compare Flag B
0
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
output compare register
• When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input capture
register
Input Capture/Output Compare Flag C
0
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
register
• When TCNT value is transferred to TGRC by input capture signal
while TGRC is functioning as input capture register
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
TGRD is functioning as input capture register
H'FE85
DISEL bit of MRB in DTC is 0
ing as output compare register
input capture signal while TGRA is functioning as
input capture register
TPU3
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