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Timer Output Timing: When compare match A or B occurs, the timer output changes as
specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same,
change to 0, change to 1, or toggle.
Figure 10-5 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B
occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10-6 shows the
timing of this operation.
φ
Compare match
signal
TCNT
Figure 10-5 Timing of Timer Output
N
Figure 10-6 Timing of Compare Match Clear
H'00
Rev. 5.00, 12/03, page 395 of 1088
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