Erase Block Register 1 (Ebr1) - Renesas H8S/2319 series Hardware Manual

Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF.
Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time.
Bit 0
P2 Description
0 Program mode cleared
1 Transition to program mode
[Setting condition]
When SWE2 = 1, and PSU2 = 1

17.14.3 Erase Block Register 1 (EBR1)

Bit : 7
EBR1 EB7
Initial value : 0
R/W : R/W
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be
erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting
more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash
memory is disabled, a read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 17-28.
6 5
EB6 EB5 EB4
0 0
R/W R/W R/W
4 3 2
EB3 EB2
0 0 0
R/W R/W
Rev. 5.00, 12/03, page 627 of 1088
(Initial value)
1 0
EB1 EB0
0 0
R/W R/W