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Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU1 (2) bit in FLMCR1 (2)
Wait (y) µs
Set P1 (2) bit in FLMCR1 (2)
Wait (z1) µs or (z2) µs or (z3) µs
Clear P1 (2) bit in FLMCR1 (2)
Wait (α) µs
Clear PSU1 (2) bit in FLMCR1 (2)
Wait (β) µs
Disable WDT
End sub
Note: 7. Write Pulse Width
Write Time (z) µs
Number of Writes (n)
1
2
3
4
5
6
7
8
9
10
11
12
13
.
.
.
998
999
1000
Note: Use a (z3) µs write pulse for additional
programming.
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
Additional program data
area (128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be
Rev. 5.00, 12/03, page 640 of 1088
*6
Store 128-byte program data in program
*5 *6
*6
data area consecutively to flash memory
*6
*6
Increment address
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
.
.
.
z2
z2
z2
NG
performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programming if they fail the
subsequent verify operation.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data
should be provided in RAM. The contents of the reprogram data and additional program data areas are modified as programming proceeds.
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of programming. See Note *7 for the pulse widths. When the additional
program data is programmed, a write pulse of (z3) µs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has
been applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 20.3.6, Flash Memory Characteristics.
Program Data Operation Chart
Original Data (D)
Verify Data (V)
0
0
1
1
0
1
Additional Program Data Operation Chart
Reprogram Data (X')
Verify Data (V)
0
0
1
1
0
1
Figure 17-45 Program/Program-Verify Flowchart
Start of programming
Start
Perform programming in the erased state.
Do not perform additional programming
Set SWE1 (2) bit in FLMCR1 (2)
on previously programmed addresses.
Wait (x) µs
*6
*4
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
*1
Sub-routine-call
Write pulse
See Note *7 for pulse width
(z1) µs or (z2) µs
Set PV1 (2) bit in FLMCR1 (2)
Wait (γ) µs
*6
H'FF dummy write to verify address
Wait (ε) µs
*6
*2
Read verify data
NG
Read data = verify
data?
m = 1
OK
NG
6 ≥ n ?
OK
Additional program data computation
Transfer additional program data to
*4
additional program data area
*3
Reprogram data computation
Transfer reprogram data to reprogram
*4
data area
128-byte
data verification
completed?
OK
Clear PV1 (2) bit in FLMCR1 (2)
Wait (η) µs
*6
NG
6 ≥ n ?
OK
Sequentially write 128-byte data in
*1
additional program data area in RAM to
flash memory
Write Pulse
*6
(z3) µs additional write pulse
NG
m = 0?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
Clear SWE1 (2) bit in FLMCR1 (2)
Wait (θ) µs
*6
End of programming
Reprogram Data (X)
1
Programming completed
0
Programming incomplete; reprogram
1
Still in erased state; no action
Additional Program Data (Y)
0
Additional programming executed
Additional programming not executed
1
Additional programming not executed
Additional programming not executed
n ← n + 1
*6
NG
n ≥ N?
OK
Wait (θ) µs
*6
Programming failure
Comments
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