Table of Contents
Advertisement
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the
result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted
in this case.
12.5
Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag
that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers
data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously: If a number of receive errors
occur at the same time, the state of the status flags in SSR is as shown in table 12-13. If there is an
overrun error, data is not transferred from RSR to RDR, and the receive data is lost.
Table 12-13 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
1
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
Notes:
: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Rev. 5.00, 12/03, page 480 of 1088
Receive Data Transfer
PER
from RSR to RDR
0
X
0
1
0
X
1
X
1
1
X
Receive Error Status
Overrun error
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error +
parity error
Advertisement
Table of Contents
