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Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB
Description
0
Interrupt requests (TGIB) by TGFB disabled
1
Interrupt requests (TGIB) by TGFB enabled
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA
Description
0
Interrupt requests (TGIA) by TGFA disabled
1
Interrupt requests (TGIA) by TGFA enabled
9.2.5
Timer Status Registers (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:
7
—
Initial value :
1
R/W
:
—
Note: * Only 0 can be written, to clear the flag.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:
7
TCFD
Initial value :
1
R/W
:
R
Note: * Only 0 can be written, to clear the flag.
Rev. 5.00, 12/03, page 326 of 1088
6
5
—
—
TCFV
1
0
R/(W) *
—
—
6
5
—
TCFU
TCFV
1
0
R/(W) *
R/(W) *
—
4
3
2
TGFD
TGFC
0
0
0
R/(W) *
R/(W) *
4
3
2
—
—
0
0
0
—
—
(Initial value)
(Initial value)
1
0
TGFB
TGFA
0
0
R/(W) *
R/(W) *
1
0
TGFB
TGFA
0
0
R/(W) *
R/(W) *
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