Renesas H8S/2319 series Hardware Manual page 95

φ
Internal address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus
Figure 2-14 On-Chip Memory Access Cycle
φ
Address bus
AS
RD
HWR, LWR
Data bus
Figure 2-15 Pin States during On-Chip Memory Access
Bus cycle
T
1
Address
Bus cycle
T
1
Unchanged
High
High
High
High-impedance state
Read data
Write data
Rev. 5.00, 12/03, page 65 of 1088