Ram Emulation Register (Ramer) - Renesas H8S/2319 series Hardware Manual

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash
memory control registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR). Writing 1 to the
FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE
to 0 designates these registers as unselected (the register contents are retained).
Bit 3
FLSHE Description
0 Flash control registers are not selected for addresses H'FFFFC4 to H'FFFFCF
1 Flash control registers are selected for addresses H'FFFFC4 to H'FFFFCF
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: Only 0 may be written to this bit.

17.23.4 RAM Emulation Register (RAMER)

Bit : 7
—
Initial value : 0
R/W : —
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 17-51. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Rev. 5.00, 12/03, page 694 of 1088
6 5
— — —
0 0
— — —
4 3 2
RAMS RAM2
0 0 0
R/W R/W
(Initial value)
1 0
RAM1 RAM0
0 0
R/W R/W