Serial Status Register (Ssr) - Renesas H8S/2319 series Hardware Manual

Bit 1—Reserved: Read-only bit, always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface
function.
Bit 0
SMIF Description
0 Smart card interface function is disabled
1 Smart card interface function is enabled
13.2.2

Serial Status Register (SSR)

Bit : 7
TDRE
Initial value : 1
R/(W) *
R/W :
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In smart card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
smart card interface mode.
Bit 4
ERS Description
0 Indicates data received normally with no error signal
[Clearing conditions]
•
Upon reset, and in standby mode or module stop mode
•
When 0 is written to ERS after reading ERS = 1
1 Indicates an error signal was sent showing detection of a parity error at the receiving
side
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
Rev. 5.00, 12/03, page 492 of 1088
6 5
RDRF ORER
0 0
R/(W) * R/(W) * R/(W) *
4 3
ERS PER TEND
0 0
R/(W) *
(Initial value)
2 1 0
MPB MPBT
1 0 0
R R R/W
(Initial value)