Register Configuration - Renesas H8S/2319 series Hardware Manual

Table 19-1 Operating Modes
Operating Transition
Mode Condition
High speed Control
mode register
Medium- Control
speed mode register
Sleep mode Instruction
Module stop Control
mode register
Software Instruction
standby
mode
Hardware Pin
standby
mode
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting
modules on the high-speed clock.
2. Some SCI registers and the A/D converter are reset, and other on-chip supporting
modules retain their states.
19.1.1

Register Configuration

Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 19-2
summarizes these registers.
Table 19-2 Power-Down Mode Registers
Name
Standby control register
System clock control register
Module stop control register H
Module stop control register L
Note: * Lower 16 bits of the address.
Rev. 5.00, 12/03, page 778 of 1088
Clearing
Condition Oscillator
Functions
Functions
Interrupt Functions
Functions
External Halted
interrupt
Halted
Abbreviation
SBYCR
SCKCR
MSTPCRH
MSTPCRL
CPU
Registers
High Function
speed
Medium Function
speed
Halted Retained
High/ Function
medium
speed
Halted Retained
Halted Undefined
R/W Initial Value
R/W H'08
R/W H'00
R/W H'3F
R/W H'FF
Modules
Registers I/O Ports
High Function High speed
speed
High/ Function High speed
medium
speed * 1
High Function High speed
speed
Halted Retained/ Retained
reset * 2
Halted Retained/ Retained
reset * 2
Halted Reset High
impedance
Address *
H'FF38
H'FF3A
H'FF3C
H'FF3D