17.17.3 Error Protection - Renesas H8S/2319 series Hardware Manual

17.17.3 Error Protection

In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR1, and EBR2
settings are retained, but program mode or erase mode is aborted at the point at which the error
occurred. Program mode or erase mode cannot be re-entered by re-setting the P1, P2, E1, or E2
bit. However, PV1, PV2, EV1, and EV2 bit setting is enabled, and a transition can be made to
verify mode.
FLER bit setting conditions are as follows:
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction (including software standby) is executed during
programming/erasing
• When the CPU loses the bus during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 17-47 shows the flash memory state transition diagram.
Rev. 5.00, 12/03, page 645 of 1088