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Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T
state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes
2
precedence and the TCFV/TCFU flag in TSR is not set.
Figure 9-57 shows the operation timing when there is contention between TCNT write and
overflow.
φ
Address
Write signal
TCNT
TCFV flag
Figure 9-57 Contention between TCNT Write and Overflow
Multiplexing of I/O Pins: In the chip, the TCLKA input pin is multiplexed with the TIOCC0 I/O
pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O
pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input,
compare match output should not be performed from a multiplexed pin.
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Rev. 5.00, 12/03, page 382 of 1088
TCNT write cycle
T
T
1
TCNT address
H'FFFF
2
TCNT write data
M
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