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TMDR3—Timer Mode Register 3
Bit
:
7
Initial value
:
1
Read/Write
:
Rev. 5.00, 12/03, page 946 of 1088
6
5
4
BFB
BFA
1
0
0
R/W
R/W
Buffer Operation A
0
1
Buffer Operation B
0
TGRB operates normally
TGRB and TGRD used together
1
for buffer operation
H'FE81
3
2
MD3
MD2
0
0
R/W
R/W
Mode
0
0
1
×
1
Notes: 1.
MD3 is a reserved bit. In a write,
it should always be written with 0.
2.
Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written
to MD2.
TGRA operates normally
TGRA and TGRC used together
for buffer operation
TPU3
1
0
MD1
MD0
0
0
R/W
R/W
0
0
Normal operation
1
Reserved
1
0
PWM mode 1
1
PWM mode 2
0
0
Phase counting mode 1
1
Phase counting mode 2
1
0
Phase counting mode 3
1
Phase counting mode 4
×
×
× : Don't care
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