System Clock Control Register (Sckcr) - Renesas H8S/2319 series Hardware Manual

19.2.2

System Clock Control Register (SCKCR)

Bit : 7
PSTOP
Initial value : 0
R/W : R/W
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ φ φ φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7 Normal
PSTOP Operating Mode
φ output (Initial value)
0
1 Fixed high
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is
disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to
the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the
division ratio. As the frequency of φ changes, the following points must be noted.
• The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the
guaranteed operation range of clock cycle time tcyc given in the AC timing table in the
Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz
does not arise.
• All internal modules basically operate on φ. Note, therefore, that time processing involving the
timers, the SCI, etc., will change when the division ratio changes. The wait time when software
standby is cleared will also change in line with a change in the division ratio.
6 5
— DIV
0 0
R/W R/W
Description
Sleep Mode
φ output
Fixed high
4 3
— — SCK2
0 0
— — R/W
Software
Standby Mode
Fixed high
Fixed high
Rev. 5.00, 12/03, page 781 of 1088
2 1 0
SCK1 SCK0
0 0 0
R/W R/W
Hardware
Standby Mode
High impedance
High impedance