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Contention between TGR Write and Input Capture: If the input capture signal is generated in
the T
state of a TGR write cycle, the input capture operation takes precedence and the write to
2
TGR is not performed.
Figure 9-54 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 9-54 Contention between TGR Write and Input Capture
TGR write cycle
T
T
1
2
TGR address
M
M
Rev. 5.00, 12/03, page 379 of 1088
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