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TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode.
10.2.3
Time Constant Registers B0 and B1 (TCORB0, TCORB1)
Bit
:
15
Initial value :
1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a
single 16-bit register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set. Note, however, that comparison is disabled during the
T
state of a TCOR write cycle.
2
The timer output can be freely controlled by these compare match signals and the settings of
output select bits OS3 and OS2 in TCSR.
TCORB0 and TCORB1 are each initialized to H'FF by a reset and in hardware standby mode.
10.2.4
Time Control Registers 0 and 1 (TCR0, TCR1)
Bit
:
7
CMIEB
Initial value :
0
R/W
:
R/W
TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at
which TCNT is cleared, and enable interrupts.
TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.
For details of this timing, see section 10.3, Operation.
TCORB0
14
13
12
11
10
1
1
1
1
6
5
CMIEA
OVIE
0
0
R/W
R/W
9
8
7
6
1
1
1
1
1
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Rev. 5.00, 12/03, page 387 of 1088
TCORB1
5
4
3
2
1
1
1
1
1
1
2
1
CKS2
CKS1
0
0
R/W
R/W
0
1
0
CKS0
0
R/W
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