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Table 17-55 Software Protection
Item
Protection by the
SCO bit
Protection by the
FKEY register
Emulation protection •
17.25.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer entering runaway during programming/erasing of the flash memory or
operations that are not according to the established procedures for programming/erasing. Aborting
programming or erasure in such cases prevents damage to the flash memory due to excessive
programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in the FCCS register is set to 1 and the device enters the error-protection state, and this aborts
the programming or erasure.
The FLER bit is set in the following conditions:
(1) When an interrupt, such as NMI, has occurred during programming/erasing
(2) When the relevant block area of flash memory is read during programming/erasing (including
a vector read or an instruction fetch)
(3) When a SLEEP instruction (including software standby mode) is executed during
programming/erasing
(4) When a bus master other than the CPU, such as DTC or BREQ, has obtained the bus right
during programming/erasing
Description
•
Clearing the SCO bit in the FCCS
register makes the device enter a
program/erase-protected state, and
this disables the downloading of the
programming/erasing programs.
•
Downloading and
programming/erasing are disabled
unless the required key code is written
in the FKEY register. Different key
codes are used for downloading and
for programming/erasing.
Setting the RAMS bit in the RAM
emulation register (RAMER) makes
the device enter a program/erase-
protected state.
Function to be Protected
Download
Program/Erase
Rev. 5.00, 12/03, page 715 of 1088
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