Register Descriptions; Smart Card Mode Register (Scmr) - Renesas H8S/2319 series Hardware Manual

13.2

Register Descriptions

Registers added with the smart card interface and bits for which the function changes are
described here.
13.2.1

Smart Card Mode Register (SCMR)

Bit : 7
—
Initial value : 1
R/W : —
SCMR is an 8-bit readable/writable register that selects the smart card interface function.
SCMR is initialized to H'F2 by a reset and in hardware standby mode. In software standby mode
and module stop mode it retains its previous state.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the SDIR bit for communication with an inverse convention card.
The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures,
see section 13.3.4, Register Settings.
Bit 2
SINV Description
0 TDR contents are transmitted as they are
Receive data is stored as it is in RDR
1 TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
6 5
— — —
1 1
— — —
4 3 2
SDIR SINV
1 0 0
R/W R/W
Rev. 5.00, 12/03, page 491 of 1088
1 0
— SMIF
1 0
— R/W
(Initial value)
(Initial value)