Renesas H8S/2319 series Hardware Manual page 442

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (φ), for input to TCNT.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow
occurs.
11.2.3 Reset Control/Status Register (RSTCSR)
Bit : 7
WOVF
Initial value : 0
R/(W) *
R/W :
Note: * Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
Rev. 5.00, 12/03, page 412 of 1088
Description
Clock
φ/2 (Initial value)
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
6 5
RSTE —
0 0
R/W R/W
Overflow Period (when φ φ φ φ = 20 MHz) *
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
4 3
— —
1 1
— —
2 1
— — —
1 1
— — —
0
1