Table of Contents
Advertisement
Level 7 interrupt?
Mask level 6
or below?
Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in
Rev. 5.00, 12/03, page 130 of 1088
Program execution state
Interrupt generated?
Yes
No
Yes
Level 6 interrupt?
No
Yes
Mask level 5
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Interrupt Control Mode 2
No
Yes
NMI?
No
No
Yes
No
Yes
No
Level 1 interrupt?
Yes
No
Mask level 0?
Yes
Hold pending
Advertisement
Table of Contents
