Buffer Operation - Renesas H8S/2319 series Hardware Manual

9.4.4

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Table 9-5 shows the register combinations used in buffer operation.
Table 9-5 Register Combinations in Buffer Operation
Channel
0
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9-16.
Buffer register
Rev. 5.00, 12/03, page 344 of 1088
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Compare match signal
Timer general
register
Figure 9-16 Compare Match Buffer Operation
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
Comparator TCNT