Renesas H8S/2319 series Hardware Manual page 949

Table A-7 Condition Code Modification
Instruction H N
ADD
ADDS — — — — —
ADDX
AND —
ANDC
BAND — — — —
Bcc — — — — —
BCLR — — — — —
BIAND — — — —
BILD — — — —
BIOR — — — —
BIST — — — — —
BIXOR — — — —
BLD — — — —
BNOT — — — — —
BOR — — — —
BSET — — — — —
BSR — — — — —
BST — — — — —
BTST — —
BXOR — — — —
CLRMAC
Z V C Definition
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Rm · Rm–1 · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4
N = Rm
Z = Z' · Rm · ...... · R0
V = Sm · Dm · Rm + Sm · Dm · Rm
C = Sm · Dm + Dm · Rm + Sm · Rm
0 — N = Rm
Z = Rm · Rm–1 · ...... · R0
Stores the corresponding bits of the result.
No flags change when the operand is EXR.
C = C' · Dn
C = C' · Dn
C = Dn
C = C' + Dn
C = C' · Dn + C' · Dn
C = Dn
C = C' + Dn
Z = Dn
— —
C = C' · Dn + C' · Dn
Cannot be used in the chip
Rev. 5.00, 12/03, page 919 of 1088