5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
:
R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating
Modes.
SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
Bit 4
Interrupt
INTM1
INTM0
Control Mode
0
0
0
1
—
1
0
2
1
—
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
Description
0
Interrupt request generated at falling edge of NMI input
1
Interrupt request generated at rising edge of NMI input
Rev. 5.00, 12/03, page 112 of 1088
6
5
—
INTM1
INTM0
0
0
—
R/W
R/W
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
4
3
2
NMIEG
LWROD
0
0
0
R/W
R/W
1
0
—
RAME
0
1
R/W
R/W
(Initial value)
(Initial value)