Renesas H8S/2319 series Hardware Manual page 496

Renesas 16-bit single-chip microcomputer
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Figure 12-11 shows an example of SCI operation for transmission using the multiprocessor
format.
Start
1
bit
0
D0
TDRE
TEND
TXI interrupt
Data written to TDR
request generated
and TDRE flag cleared to
0 in TXI interrupt handling
routine
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
• Multiprocessor serial data reception
Figure 12-12 shows a sample flowchart for multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
Rev. 5.00, 12/03, page 466 of 1088
Multi-
proces-
Data
sor
bit
D1
D7
0/1
1 frame
Figure 12-11 Example of SCI Transmit Operation
Stop
Start
bit
bit
1
0
D0
D1
TXI interrupt
request generated
Multi-
Data
Stop
proces-
sor bit
bit
Idle state
D7
0/1
1
(mark state)
TEI interrupt
request generated
1

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