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Figure 6-14 shows an example of wait state insertion timing.
φ
Address bus
Read
Data bus
HWR, LWR
Write
Data bus
indicates the timing of WAIT pin sampling.
Note:
The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT
input disabled.
T
1
WAIT
AS
RD
Figure 6-14 Example of Wait State Insertion Timing
By WAIT pin
By program wait
T
T
T
2
w
Write data
Rev. 5.00, 12/03, page 169 of 1088
T
T
w
w
3
Read data
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