Renesas H8S/2319 series Hardware Manual page 310

Port F Data Register (PFDR)
Bit : 7
PF7DR
Initial value : 0
R/W : R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).
PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after
in software standby mode.
Port F Register (PORTF)
Bit : 7
PF7
— *
Initial value :
R/W : R
Note: * Determined by state of pins PF7 to PF0.
PORTF is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of
output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state after in software standby mode.
Port Function Control Register 1 (PFCR1)
Bit : 7
CSS17
Initial value : 0
R/W : R/W
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin. For
details, see section 8.12, Port G.
Rev. 5.00, 12/03, page 280 of 1088
6 5
PF6DR PF5DR
0 0
R/W R/W
6 5
PF6 PF5
— * — *
R R
6 5
CSS36 PF1CS5S PF0CS4S
0 0
R/W R/W
4 3
PF4DR PF3DR
0 0
R/W R/W
4 3
PF4 PF3
— * — *
R R
4 3
A23E
0 1
R/W R/W
2 1
PF2DR PF1DR
0 0
R/W R/W
2 1
PF2 PF1
— * — *
R R
2 1
A22E A21E
1 1
R/W R/W
0
PF0DR
0
R/W
0
PF0
— *
R
0
A20E
1
R/W