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17.1
Overview
The Group has 512, 384, 256, or 128 kbytes of on-chip flash memory, or 512, 256, 128, or 32
kbytes of on-chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus,
enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded
up, and processing speed increased.
The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the
EAE bit in BCRL.
The flash memory version of the chip can be erased and programmed with a PROM programmer,
as well as on-board.
17.1.1
Block Diagram
Figure 17-1 shows a block diagram of 512 kbytes of on-chip ROM.
Section 17 ROM
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'000000
H'000002
H'07FFFE
Figure 17-1 Block Diagram of ROM (512 kbytes)
H'000001
H'000003
H'07FFFF
Rev. 5.00, 12/03, page 551 of 1088
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