Renesas H8S/2319 series Hardware Manual page 197

φ
Address bus
CSn
AS
RD
D to D
Read
15
D to D
7
HWR
LWR
Write
D to D
15
D to D
7
Note: n = 0 to 7
Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
T
1
8
0
8
0
Bus cycle
T
2
Valid
Valid
Rev. 5.00, 12/03, page 167 of 1088
T
3
Valid
Valid