Renesas H8S/2319 series Hardware Manual page 839

(4) Timing of On-Chip Supporting Modules
Table 20-7 Timing of On-Chip Supporting Modules
Condition A: V = 2.7 V to 3.6 V, AV
CC
0 V, φ = 2 MHz to 20 MHz, T
T = –40°C to 85°C (wide-range specifications)
a
Condition B: V = 3.0 V to 3.6 V, AV
CC
0 V, φ = 2 MHz to 25 MHz, T
T = –40°C to 85°C (wide-range specifications)
a
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
8-bit timer Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock
pulse width
WDT Overflow output delay time
= 2.7 V to 3.6 V, V
CC
a
= 3.0 V to 3.6 V, V
CC
a
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single-edge t
TCKWH
specification
Both-edge t
TCKWL
specification
t
TMOD
t
TMRS
t
TMCS
Single-edge t
TMCWH
specification
Both-edge t
TMCWL
specification
t
WOVD
= 2.7 V to AV
ref
= –20°C to 75°C (regular specifications),
= 3.0 V to AV
ref
= –20°C to 75°C (regular specifications),
Condition A Condition B
Min Max Min
— 50 —
30 — 25
30 — 25
— 50 —
30 — 25
30 — 25
1.5 — 1.5
2.5 — 2.5
— 50 —
30 — 25
30 — 25
1.5 — 1.5
2.5 — 2.5
— 50 —
Rev. 5.00, 12/03, page 809 of 1088
, V = AV
CC SS SS
, V = AV
CC SS SS
Test
Max Unit Conditions
40 ns Figure 20-13
— ns
— ns
40 ns Figure 20-14
— ns
— ns Figure 20-15
— t
cyc
— t
cyc
40 ns Figure 20-16
— ns Figure 20-18
— ns Figure 20-17
— t
cyc
— t
cyc
40 ns Figure 20-19
=
=