Renesas H8S/2319 series Hardware Manual page 734

When hardware standby mode is entered during download processing, the normal download
cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
Since a stack area of a maximum 128 bytes is used, the area must be saved before setting the
SCO bit to 1.
If flash memory is accessed by the DTC or BREQ during downloading, the operation cannot
be guaranteed. Therefore, access by the DTC or BREQ must not be executed.
(d) FKEY is cleared to H'00 for protection.
(e) The value of the DPFR parameter must be checked and the download result must be
confirmed.
A recommended procedure for confirming the download result is shown below.
• Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
• If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
• If the value of the DPFR parameter is different from before downloading, check the SS bit
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY register setting were normal, respectively.
(f) The operating frequency is set to the FPEFEQ parameter for initialization.
• The current frequency of the CPU clock is set to the FPEFEQ parameter (general register:
ER0).
The settable range of the FPEFEQ parameter is 2 MHz to 25 MHz.
When the frequency is set out of this range, an error is returned to the FPFR parameter of
the initialization program and initialization is not performed. For details on the frequency
setting, see the description in 17.23.2 (a) Flash programming/erasing frequency parameter
(FPEFEQ: general register ER0 of CPU).
Rev. 5.00, 12/03, page 704 of 1088