Renesas H8S/2319 series Hardware Manual page 196

φ
Address bus
CSn
D to D
Read
15
D to D
7
HWR
LWR
Write
D to D
15
D to D
7
Note: n = 0 to 7
Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Rev. 5.00, 12/03, page 166 of 1088
T
1
AS
RD
8
0
8
0
Bus cycle
T
2
High
High impedance
Valid
T
3
Invalid
Valid